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? semiconductor components industries, llc, 2015 march, 2015 ? rev. 4 1 publication order number: kai?0373/d kai-0373 768 (h) x 484 (v) interline ccd image sensor description the kai?0373 is a high-performance silicon char ge-coupled device (ccd) designed for video image sensing and electronic still photography. the device is built using an advanced true two-phase, double-polysilicon, nmos ccd technology. the p+npn? photodetector elements eliminate image lag and reduce image smear while providing anti-blooming protection and electronic-exposure control. the total chip size is 9.9 (h) mm 7.7 (v) mm. the kai?0373 comes in monochrome versions, with an option with microlens for sensitivity improvement. table 1. general specifications parameter typical value architecture interline transfer cdd; progressive scan number of active pixels 768 (h) 484 (v) number of outputs 1 pixel size 11.6 m(h) 13.6 m (v) active image size 8.91 mm (h) 6.58 mm (v), 11.1 mm (diagonal), 2/3 optical format aspect ratio 3:2 output sensitivity 9 v/e ? photometric sensitivity kai?0373?aba 2.2 v/lux?sec charge capacity 55 ke ? maximum pixel clock speed 14.32 mhz maximum frame rate 30 fps package type cerdip package size 0.800 [20.32 mm] width 1.200 [30.48 mm] length package pins 24 package pin spacing 0.100 (2.54 mm) note: all parameters are specified at t = 40 c unless otherwise noted. features ? high resolution ? high sensitivity ? high dynamic range ? low noise architecture ? high frame rate ? binning capability for higher frame rate ? electronic shutter application ? intelligent traffic systems ? surveillance www.onsemi.com figure 1. kai?0373 interline ccd image sensor see detailed ordering and shipping information on page 2 o f this data sheet. ordering information
kai?0373 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kai?0373?aaa?cp?ba monochrome, no microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), standard grade kai?0373?aaa serial number kai?0373?aba?cb?ae monochrome, telecentric microlens, cerdip package (sidebrazed), sealed clear cover glass (no coatings), engineering grade kai?0373?aba serial number kai?0373?aba?cb?ba monochrome, telecentric microlens, cerdip package (sidebrazed), sealed clear cover glass (no coatings), standard grade kai?0373?aba?cp?ba monochrome, telecentric microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), standard grade see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kai?0373 www.onsemi.com 3 device description architecture figure 2. block diagram ?? ?? ??? ??? v2b v1b v2a v1a kai?0373 usable active image area 768 (h) 484 (v) 11.6 m 13.6 m pixels 768 active pixels/line 768 5 dark rows 12 dark columns v1a v2a v1b v2b ltsh h1 h2 r v rd vlg v dd v out v ss well subs og 8 12 2 = 791 pixels/line the kai?0373 consists of 371, 712 photodiodes, 768 vertical (parallel) ccd shift registers (vccds), one horizontal (serial) ccd shift register and one output amplifier. the advanced, progressive-scan architecture of the device allows the entire image area to be read out in a single scan. the pixels are arranged in a 768 (h) 484 (v) array in which an additional 12 columns and 5 rows of light shielded pixels are added as dark reference. image acquisition an electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photosite. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. when the photodiode?s charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. charge transport the accumulated or integrated charge from each photodiode is transported to the output by a three step process. the charge is first transported from the photodiodes to the vccds by applying a large positive voltage to the phase-one vertical clock ( v2). this reads out every row, or line, of photodiodes into the vccds. the charge is then transported from the vccds to the hccds line by line. finally, the hccds transport these rows of charge packets to the output structures pixel by pixel. on each falling edge of the horizontal clock, h2, these charge packets are dumped over the output gate (og, figure 3) onto the floating diffusion (fd figure 3). both the horizontal and vertical shift registers use traditional two-phase complementary clocking for charge transport. t ransfer to the horizontal cdd begins when v2 is brought low (and v1 high) causing a line of charge to transfer from v2 to v1 and subsequently into the horizontal register. the sequence completes when v1 is brought low before the horizontal ccd reads the first line of charge.
kai?0373 www.onsemi.com 4 output structure charge packets contained in the horizontal register are dumped pixel by pixel, onto the floating diffusion output node whose potential varies linearly with the quantity of charge in each packet. the amount of potential change is determined by the expression v fd = q/c fd . a three stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. the translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of v/e ? . after the signal has been sampled off-chip, the reset clock ( r) removes the charge from the floating diffusion and resets its potential to the reset-drain voltage (vrd). figure 3. output structure fd = floating diffusion fd v out v dd r vrd sub well vlg v ss electronic shutter the kai?0373 provides a structure for the prevention of blooming which may be used to realize a variable exposure time as well as performing the anti-blooming function. the anti-blooming function limits the charge capacity of the photodiode by draining excess electrons vertically into the substrate (hence the name vertical overflow drain or vod). this function is controlled by applying a large potential to the device substrate (device terminal sub). if a sufficiently large voltage pulse (ves 40 v) is applied to the substrate, all photodiodes will be emptied of charge through the substrate, beginning the integration period. after returning the substrate voltage to the nominal value, charge can accumulate in the diodes and the charge packet is subsequently readout onto the vccd at the next occurrence of the high level on v2. the integration time is then the time between the falling edges of the substrate shutter pulse and v2. this scheme allows electronic variation of the exposure time by a variation in the clock timing while maintaining a standard video frame rate. application of the large shutter pulse must be avoided during the horizontal register readout or an image artifact will appear due to feedthrough. the shutter pulse ves must be ?hidden? in the horizontal retrace interval. the integration time is changed by skipping the shutter pulse from one horizontal retrace interval to another. the smear specification is not met under electronic shutter operation. under constant light intensity and spot size, if the electronic exposure time is decreased, the smear signal will remain the same while the image signal will decrease linearly with exposure. smear is quoted as a percentage of the image signal and so the percent smear will increase by the same factor that the integration time has decreased. this effect is basic to interline devices. extremely bright light can potentially harm solid state imagers such as charge-coupled devices (ccds). refer to application note using interline ccd image sensors in high intensity visible lighting conditions .
kai?0373 www.onsemi.com 5 on-chip gate protection gates og, r, vlg, v ss , h1 and h2 are internally connected to transistors as shown in figure 4 to provide active esd protection. for the protection to work, pin 11 (horizontal esd well) and pin 13 (vertical esd well) must be biased to ?10 v. the esd bias must be at least 1 v more negative that h1 and h2 during sensor operation and during camera power turn on. this sensor, like most other mos-based image sensors, is extremely sensitive to electrostatic discharge (esd) damage. the handling and environment of the sensor must be controlled to protect this device from esd damage. figure 4. internal protection circuit for h1 and h2 horizontal esd well pin connection gate snap-back field fet
kai?0373 www.onsemi.com 6 physical description pin description and device orientation figure 5. pin description pin 1 locator side view of package 12345 og 1 r2 vrd 3 vss 4 vlg 5 vout 6 vdd 7 well 8 h2 9 h1 10 esd 11 nc 12 24 v2a 23 v1a 22 v2b 21 v1b 20 well 19 sub 18 ltsh 17 v1a 16 v2a 15 v1b 14 v2b 13 esd pixel 1, 1 table 3. pin description pin name description 1 og output gate 2 r reset clock 3 vrd reset drain 4 vss output amplifier return 5 vlg output amplifier load gate 6 vout video output 7 vdd output amplifier supply 8 well ground 9 h2 horizontal ccd clock ? phase 2 10 h1 horizontal ccd clock ? phase 1 11 esd horizontal esd well 12 nc no connect pin name description 13 esd horizontal esd well 14 v2b vertical ccd clock ? phase 2 15 v1b vertical ccd clock ? phase 1 16 v2a vertical ccd clock ? phase 2 17 v1a vertical ccd clock ? phase 1 18 ltsh lightshield 19 sub substrate 20 well ground 21 v1b vertical ccd clock ? phase 1 22 v2b vertical ccd clock ? phase 2 23 v1a vertical ccd clock ? phase 1 24 v2a vertical ccd clock ? phase 2 1. the pins are on a 0.100 spacing. 2. pins 14, 16, 22, and 24 must be connected together ? only one phase 2 clock driver is required. 3. pins 15, 17, 21, and 23 must be connected together ? only one phase 1 clock driver is required.
kai?0373 www.onsemi.com 7 imaging performance all following values were derived for the kai?0373?aba series devices (with microlens array) using nominal operating conditions and the recommended timing. unless otherwise stated, readout time = 33 ms, integration time = 33 ms, no electronic shutter pulse is applied, and sensor temperature = 40 c. correlated double sampling of the output is assumed and recommended. defects are excluded from the following tests and the signal output is referenced to the dark pixels at the end of each line unless otherwise specified. specifications table 4. ccd description symbol min. nom. max. unit notes saturation signal ? vccd ne ? sat 55 ? ? ke ? output saturation signal v sat 500 ? ? mv 1, 2, 6 photodiode dark current i d ? ? 0.5 na charge transfer efficiency cte ? 0.99999 ? 2, 3 horizontal ccd frequency f h ? 14.3 ? mhz image lag il ? negligible ? blooming margin x ab ? 300 ? 4, 6 smear smr ? 0.01 0.04 % 5 1. v sat is the mean value at saturation as measured at the output of the device with x ab = 300. this value is guaranteed only when v sub =v ab as indicated on the sensor package. v sat can be varied by adjusting v sub . 2. measured at the sensor output. 3. with stray load capacitance of cl = 10pf between the output and ac ground. 4. x ab represents the increase above the saturation-irradiance level (h sat ) that the device can be exposed to before blooming of the vertical shift register will occur. it should be noted that v out rises above v sat for irradiance levels above h sat . 5. measured under 10% (~48 lines) image height illumination with white light source and without electronic shutter operation and below v sat . 6. it should be noted that there is a tradeoff between x ab and v sat . table 5. output amplifier @ v dd = 15 v, v ss = 0.5 v description symbol min. nom. max. unit notes output dc offset v odc 5 6.3 7.5 v power dissipation p d ? 75 ? mw output amplifier bandwidth f? 3db 100 ? ? mhz 1 sensitivity (output referred) v o / n ? 9 ? v/e ? off-chip load c l ? ? 10 pf 1. with stray output load capacitance of c l = 10 pf between output and ac ground. table 6. general description symbol min. nom. max. unit notes total sensor noise ne ? total ? 55 ? e ? rms 1 dynamic range dr ? 60 ? db 2 1. includes amplifier noise, dark pattern noise and dark current shot noise at data rates of 14 mhz. 2. uses 20 log (ne ? sat / ne ? total ) where ne ? sat refers to the vertical ccd saturation signal.
kai?0373 www.onsemi.com 8 table 7. electro-optical for kai?0373?aba monochrome with microlens description symbol min. nom. max. unit notes saturation exposure e sat ? 0.044 ? j/cm 2 1 peak quantum efficiency qe ? 35 ? % 2 photoresponse non-uniformity prnu ? ? 2 % rms 3 photoresponse non-linearity prnl ? ? 2 % photoresponse shading r s ? ? 10 % 4 1. for = 530 nm wavelength, and n sat =55ke ? . 2. refer to typical values from figure 8. 3. for a 100 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal. saturation signal, v sat , is the output voltage at the knee of the output vs illumination curve as shown in figure 6. 4. this is the global variation in chip output across the entire chip measured at 80% saturation and is expressed as a percentag e of the mean pixel value. saturation signal, v sat , is the output voltage at the knee of the output vs illumination curve as shown in figure 6. figure 6. typical kai?0373 photoresponse 0 100 200 300 400 500 600 700 800 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 sensor plane irradiance ? h ? (arb) (h sat , v sat ) output signal ? v out ? (mv)
kai?0373 www.onsemi.com 9 defect definitions all values are derived under normal operating conditions at 40 c operating temperature. table 8. defect definitions defect type defect definition number allowed notes defective pixel under uniform illumination with mean pixel output of 400 mv, a defective pixel deviates by more than 15% from the mean value of all active pixels in its section. 5 1, 2 bright defect under dark field conditions, a bright defect deviates more than 15 mv from the mean value of all pixels in its section. 0 1, 2 cluster defect two or more vertically or horizontally adjacent defective pixels. 0 2 1. sections are 256 (h) 242 (v) pixel groups, which divide the imager into six equal areas as shown below. 2. test conditions: junction temperature = 40 c, integration time = 33 ms and readout time = 33 ms. figure 7. (1,484) (1,1) (768,1) (768,484)
kai?0373 www.onsemi.com 10 typical performance curves figure 8. monochrome with microlens quantum efficiency 0% 5% 10% 15% 20% 25% 30% 35% 40% 400 450 500 550 600 650 700 750 800 850 900 950 1000 wavelength (nm) quantum efficiency (%) figure 9. monochrome, no microlens, no cover glass quantum efficiency 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 wavelength (nm) quantum efficiency (%) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
kai?0373 www.onsemi.com 11 operation absolute maximum ratings absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. if the level or the condition is exceeded, the device will be degraded and may be damaged. table 9. absolute maximum ratings rating description min. max. unit notes temperature (@ 10% 5% rh) operation to specification 25 40 c operation without damage ?25 55 c storage ?25 70 c voltage (between pins) sub?well 0 50 v 1, 3 vrd, vdd, and vss?well 0 25 v 2 all clocks ? well ? 17 v 2 v1 ? v2 ? 17 v 2 h1 ? h2 ? 17 v 2 h1, h2 ? v2 ? 17 v 2 h2 ? og ? 17 v 2 all clocks ? ltsh ? 17 v 2 vlg, og ? well ? 17 v 2 all gates ? ltsh ? 17 v 2 current output bias current (i dd ) ? 10 ma capacitance output load capacitance (c load ) ? 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. under normal operating conditions the substrate voltage should be above +7 v, but may be pulsed to 40 v for electronic shutteri ng. 2. care must be taken in handling so as not to create static discharge which may permanently damage the device. 3. refer to application note using interline ccd image sensors s in high intensity visible lighting conditions . dc bias operating conditions table 10. dc bias operating conditions description symbol min. nom. max. unit notes output gate og 1.5 2 2.5 v reset drain v rd 10 10.5 11 v output amplifier return v ss 0.4 0.5 0.6 v output amplifier load gate v lg 1.7 2 2.5 v output amplifier supply v dd 14.5 15 15.5 v well well ? 0 ? v lightshield ltsh ? 0 ? v substrate sub 7 v ab 25 v 1, 4 output bias current i out 3 5 7 ma 2 esd bias esd ? ?10 ? v 3 1. the operating value of the substrate voltage, v ab , will be marked on the shipping container for each device. the substrate is clocked in electronic shutter mode operation. a shutter pulse with voltage less than 50 v for less than 100 s is allowed. see ac clock level conditions and ac timing requirements. well and substrate biases should be established before other gate and diode potentials are applied. 2. a 1.8 k resistor between v out and ground is recommended to obtain i out = 5 ma. v out must not be shorted to ground. 3. pins 11 and 13 are biased to ?10 v. the esd bias must be at least 1 v more negative than h1 and h2 during sensor operation and during camera power turn on. 4. refer to application note using interline ccd image sensors in high intensity visible lighting conditions .
kai?0373 www.onsemi.com 12 ac operating conditions table 11. clock levels description symbol min. nom. max. unit notes vertical ccd clocks ? high v1h, v2h 14.5 14.7 15 v 1 vertical ccd clocks ? mid v1m, v2m ?0.5 ?0.2 0 v 1 vertical ccd clocks ? low v1l, v2l ?9 ?8 ?7 v 1 horizontal ccd clocks ? high h1h, h2h 1 2 3 v 1 horizontal ccd clocks ? low h1l, h2l ?10 ?9 ?8 v 1 reset clock ? high rh 7 8 9 v reset clock ? low rl 2 3 4 v for electronic shutter pulse only ves (sub) 40 42 45 v 2, 3 1. for best results, the ccd clock swings must be maintained at (or greater than) the values indicted by the nominal level condi tions noted above. 2. this pulse, used only for electronic shutter mode operation, is applied to the substrate, as described in the electronic shutter section of this document. dynamic resistance is 3 k and typical dc current is 3 ma at vsub = 40 v. 3. refer to application note using interline ccd image sensors in high intensity visible lighting conditions . clock line capacitances table 12. clock line capacitances description symbol typical unit vertical ccd clocks ? well c v1, v2 (a, b combined) 10 nf vccd clock phase 1 ? vccd clock phase 2 c v1 ? v2 (a, b combined) 1.5 nf horizontal ccd clocks ? well c h1, h2 150 pf hccd clock phase 1 ? hccd clock phase 2 c h1 ? h2 60 pf reset clock ? well c r 5 pf for electronic shutter pulse c sub 400 pf
kai?0373 www.onsemi.com 13 timing table 13. requirements and characteristics description symbol min. nom. max. unit notes vertical high level duration t vh 5 17 20 s vertical transfer time t v ? 2.8 ? s vertical pedestal delay t vpd 10 ? ? s horizontal delay t hd 5.3 ? ? s reset duration t r 15 20 25 ns 1 horizontal clock frequency f h ? ? 14.32 mhz line time t l ? 63.5 ? s vertical delay t vd 200 ? ? ns horizontal delay with electronic shutter t hves 1 ? ? s clamp delay t cd ? ? ? ns 2 sample delay t sd ? ? ? ns 2 electronic shutter pulse duration t es 4 5 ? s 3 1. the rising edge of r should be coincident with the rising edge of h2, within 5 ns. 2. the clamp delay and sample delay should be adjusted for optimum results. 3. this pulse is used only with electronic shuttering and should not be used during horizontal readout. the electronic shutter p ulse should be hidden in the horizontal retrace interval. frame timing figure 10. frame timing 525 523 524 525 0 vertical overclocking 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v1 (a&b) v2 (a&b) ves (sub) v1 (a&b) v2 (a&b) 1 line time = t l = 63.5 s (electronic shutter mode only) integration time = t int t vpd t l t vh t vpd note: when no electronic shutter is used, the integration time is equal to the frame time.
kai?0373 www.onsemi.com 14 line timing figure 11. line timing v1 v2 t l = 63.5 s t hd t vd 1 9 10 777 778 789 790 791 empty shift register phases dark reference pixels photoactive pixels t v 1 line= 791 pixels h1 h2 r 55.31 s h1/ h2 count line content
kai?0373 www.onsemi.com 15 pixel timing figure 12. pixel timing reference 1 count = 1 pixel 69.8 ns signal reference signal t r h1 t sd t cd h2 r vout clamp sample video after correlated double sampling (inverted) electronic shutter timing figure 13. electronic shutter timing v2 t int t vd h1 ves (sub) t hd t v t vh t hves t es
kai?0373 www.onsemi.com 16 ccd clock waveform conditions table 14. ccd clock waveform conditions description symbol t wh t wl t r t f unit note vertical ccd clocks ? phase 1 v1m 2.8 59.8 0.6 0.3 s 1 vertical ccd clocks ? phase 2 v2m 60 2.5 0.5 0.5 s 1 vertical ccd clocks ? phase 2, high v2h 17 ? 0.5 0.5 s 1 horizontal ccd clocks ? phase 1 h1 25 27 8.5 8.5 ns 1 horizontal ccd clocks ? phase 2 h2 25 27 8.5 8.5 ns 1 reset clock r 20 40 4 5 ns 1 for electronic shutter pulse only ves (sub) 5 ? 0.2 0.2 s 1 1. typical values measured with clocks connected to image sensor device. figure 14. ccd clock waveform low 0% high 100% 90% 10% t wl t wh t f t r
kai?0373 www.onsemi.com 17 storage and handling table 15. storage conditions item description min. max. unit conditions notes operation to specification temperature 25 40 c @ 10% 5% rh 1, 2 humidity 10 5 86 5 % rh @ 36 2 c temp. 1, 2 operation without damage temperature ?25 55 c @ 10% 5% rh 2, 3 storage temperature ?25 70 c @ 10% 5% rh 2, 4 humidity ? 90 5 % rh @ 49 2 c temp. 2, 4 1. the image sensor shall meet the specifications of this document while operating at these conditions. 2. the tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy. 3. the image sensor shall continue to function but not necessarily meet the specifications of this document while operating at t he specified conditions. 4. the image sensor shall meet the specifications of this document after storage for 15 days at the specified conditions. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on environmental exposure, please download the using interline ccd image sensors in high intensity lighting conditions application note (and9183/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kai?0373 www.onsemi.com 18 mechanical information completed assembly figure 15. completed assembly 1. see ordering information for marking code. 2. cover glass is manually placed and visually aligned over die ? location accuracy is not guaranteed. 3. units: inches [mm]. notes:
kai?0373 www.onsemi.com 19 die to package alignment figure 16. die to package alignment
kai?0373 www.onsemi.com 20 glass figure 17. glass drawing 1. dust/scratch count: 10 microns max 2. epoxy thickness: 0.002 ? 0.005 3. glass: schott d?263t eco or equivalent 4. units: inches notes: 4x c 0.020 epoxy 8x c 0.008
kai?0373 www.onsemi.com 21 glass transmission figure 18. glass transmission 0 10 20 30 40 50 60 70 80 90 100 200 300 400 500 600 700 800 900 wavelength (nm) transmission (%) on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 kai?0373/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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